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Document Title: 5
User’s Manual for the GPS Orion-S/-HD Receiver
Document No. Issue 1.0
GTN-MAN-0110 June 22, 2003
DLR/GSOCNo part of this document shall be reproduced in any form or disclosed to third parties without prior authorization.
2. Receiver Hardware
2.1 Main Board
A block diagram of the GPS Orion receiver main board is shown in Fig. 2.1 ([4]). The receiver
is designed to work with an active antenna and +5 V power supply for the preamplifier is pro-
vided on the central antenna feed.
Fig 2.1 Block diagram of the GPS Orion receiver main board (from [4])
After passing an R/F ceramic filter, the L1 signal (1575.42 MHz) is down-converted and digi-
tized in the GP2015 front-end chip [7]. An external discrete filter and a DW9255 SAW filter [8]
are used to filter the first (175.42 MHz) and second (35.42 MHz) intermediate frequencies,
while an on-chip filter is used for the third analog IF (4.31 MHz). Finally, the signal is digitized
and sampled to create a digital IF of 1.405 MHz with 2-bit quantization. The fundamental
reference frequency for the mixing process is provided by a 10.0 MHz TCXO with a specified
stability of 2.5 ppm. It also used to derive a 40 MHz clock frequency for the correlator.
The subsequent signal processing is performed in the GP2021 correlator chip [9], which pro-
vides 12 fully independent C/A code correlator channels. It also offers two UART ports for
external I/O as well basic memory management capabilities that can be used when working
with the ARM micro-processor. The GP2021 chip furthermore maintains a low accuracy real-
time clock fed by a 32.568 kHz crystal. It also derives a 20 MHz clock frequency for the ARM
processor.
All software tasks operate in the 32-bit P60ARM-B micro-processor [10] that provides a peak
performance of 20 MIPS and has a typical spare capacity of 35% at 1 Hz navigation rate and
25% at 2 Hz. Upon start-up (or a reset) of the receiver, a boot loader (stored in EPROM) is
activated that copies the executable code and initialisation data from the EPROM into the