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511
BBus DMA Controller
within each DMA module. The offsets allow address bits [08:05] to encode
the DMA channel number.
Offset Description
9000 0000 / 9011 0000 DMA Channel 1 Buffer Descriptor Pointer
9000 0020 / 9011 0020 DMA Channel 2 Buffer Descriptor Pointer
9000 0040 / 9011 0040 DMA Channel 3 Buffer Descriptor Pointer
9000 0060 / 9011 0060 DMA Channel 4 Buffer Descriptor Pointer
9000 0080 / 9011 0080 DMA Channel 5 Buffer Descriptor Pointer
9000 00A0 / 9011 00A0 DMA Channel 6 Buffer Descriptor Pointer
9000 00C0 / 9011 00C0 DMA Channel 7 Buffer Descriptor Pointer
9000 00E0 / 9011 00E0 DMA Channel 8 Buffer Descriptor Pointer
9000 0100 / 9011 0100 DMA Channel 9 Buffer Descriptor Pointer
9000 0120 / 9011 0120 DMA Channel 10 Buffer Descriptor Pointer
9000 0140 / 9011 0140 DMA Channel 11 Buffer Descriptor Pointer
9000 0160 / 9011 0160 DMA Channel 12 Buffer Descriptor Pointer
9000 0180 / 9011 0180 DMA Channel 13 Buffer Descriptor Pointer
9000 01A0 / 9011 01A0 DMA Channel 14 Buffer Descriptor Pointer
9000 01C0 / 9011 01C0 DMA Channel 15 Buffer Descriptor Pointer
9000 01E0 / 9011 01E0 DMA Channel 16 Buffer Descriptor Pointer
9000 0010 / 9011 0010 DMA Channel 1 Control register
9000 0030 / 9011 0030 DMA Channel 2 Control register
9000 0050 / 9011 0050 DMA Channel 3 Control register
9000 0070 / 9011 0070 DMA Channel 4 Control register
9000 0090 / 9011 0090 DMA Channel 5 Control register
9000 00B0 / 9011 00B0 DMA Channel 6 Control register
9000 00D0 / 9011 00D0 DMA Channel 7 Control register
9000 00F0 / 9011 00F0 DMA Channel 8 Control register
9000 0110 / 9011 0110 DMA Channel 9 Control register
Table 311: DMA Control and Status register address map
