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85
Working with the CPU
Fine page tables, which have 1024 entries and split the 1 MB that the table
describes into 1 KB blocks.
Figure 27: First-level descriptor
Table 32 shows first-level descriptor bit assignments.
31 20 19 12 11 10 9 8 012345
00
0
0
1
1
11
1
1
1
CB
Domain
Domain
Domain
AP
Coarse page table base address
Section base address
Fine page table base address
Fault
Coarse page table
Section
Fine page table
Bits
Section Coarse Fine Description
[31:20] [31:10] [31:12] Forms the corresponding bits of the physical address.
[19:12] ---- ---
SHOULD BE ZERO
[11:10] --- --- Access permission bits. See "Access permissions and
domains" on page 79 and "Fault Address and Fault Status
registers" on page 96 for information about interpreting the
access permission bits.
9 9 [11:9]
SHOULD BE ZERO
[8:5] [8:5] [8:5] Domain control bits
444Must be 1.
[3:2] --- --- Bits C and B indicate whether the area of memory mapped
by this page is treated as write-back cachable, write-
through cachable, noncached buffered, or noncached
nonbuffered.
--- [3:2] [3:2]
SHOULD BE ZERO
Table 32: Priority encoding of fault status
