Ethernet Control and Status registers
394
NS9750 Hardware Reference
Register bit assignment
Transmit Buffer Descriptor Pointer Offset register
Address: A060 0A38
Register bit assignment
Bits Access Mnemonic Reset Description
D31:11 N/A Reserved N/A N/A
D10:00 R RXDOFF 0x000 Contains an 11-bit byte offset from the start of the pool D
ring. The offset is updated at the end of the RX packet, and
will have the offset to the next buffer descriptor that will
be used. RXDOFF can be used to determine where the
RX_RD logic will put the next packet.
Table 248: RX_D Buffer Descriptor Pointer Offset register
Bits Access Mnemonic Reset Description
D31:10 N/A Reserved N/A N/A
D09:00 R TXOFF 0x000 Contains a 10-bit byte offset from the start of the transmit
ring in the TX buffer descriptor RAM. The offset is
updated at the end of the TX packet, and will have the
offset to the next buffer descriptor that will be used.
TXOFF can be used to determine from where the
TX_WR
logic will grab the next packet.
Table 249: TX Buffer Descriptor Pointer Offset register
Reserved
TXOFF
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
Reserved
