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System-level interfaces
8
NS9750 Hardware Reference
System-level interfaces
Figure 1 shows the NS9750 system-level interfaces.
Figure 1: System-level hardware interfaces
Ethernet MII/RMII interface to external PHY
System memory interface
– Glueless connection to SDRAM
– Glueless connection to buffered PC100 DIMM
– Glueless connection to SRAM
– Glueless connection to Flash memory or ROM
PCI muxed with CardBus interface
USB host or device interface
I
2
C interface
50 GPIO pins muxed with:
– Four 8-pin-each serial ports, each programmable to UART or SPI
NS9750
I
2
C
Clocks & Reset
JTAG
Ethernet
Controls
Data
Address
PCI/CardBus
Power & Ground
GPIO
System
Memory
USB Host or Device
Serial
1284
LCD
Ext. DMA
Ext. IRQ
Timers/Counters
USB Host control