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PCI-to-AHB Bridge
CardBus Socket Event (see "CardBus Socket Event register" on page 446)
CardBus Socket Mask (see "CardBus Socket Mask register" on page 447)
CardBus Socket Present State (see "CardBus Socket Present State register"
on page 448)
CardBus Socket Force Event (see "CardBus Socket Force Event register" on
page 451)
CardBus Socket Control (see "CardBus Socket Control register" on page 454)
CardBus interrupts
The dedicated CINT# signal on the CardBus is connected directly to the interrupt
controller in the System Control module, as Interrupt #10 (that is, the same as the
INTA# signal for the PCI bus). Table 286 shows the CardBus-related maskable interrupt
conditions that are reported to the System Control module’s interrupt controller
through the PCI arbiter’s interrupt.
Bit field Register
CSTSCHG_CHG CardBus Socket Event
CCD1_CHG CardBus Socket Event
CCD2_CHG CardBus Socket Event
PWR_CHG CardBus Socket Event
REQ_INTGATE CardBus Miscellaneous Support
CCLKRUN PCI Arbiter Interrupt Status
Table 286: CardBus interrupt sources
