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Chapter 54 Flash Memory
3.Configuration
3. Configuration
Figure 3-1 Block Diagram (32bit flash)
Figure 3-2 Block Diagram (64bit flash)
FLASH memory
Control signal
A0 to A17
DQ0 to DQ15
Control signal
Control signal
A0 to A17
Address
DQ0 to DQ15
Data
CPU
FLASH interface
Control
signal
Address
Data
Interface
with
FLASH
writer
(when in
FLASH
mode)
CPU
CPU core
A0 to A20
DQ0 to DQ31
DQ0 to DQ31
A0 to A20
32-bit
32-bit
16-bit
FLASH memory
Control signal
A0 to A17
DQ0 to DQ15
Control signal
Control signal
A0 to A17
Address
DQ0 to DQ15
Data
CPU
FLASH interface
Control
signal
Address
Data
Interface
with
FLASH
writer
(when in
FLASH
mode)
CPU
CPU core
A0 to A20
DQ0 to DQ63
DQ0 to DQ63
A0 to A20
64-bit
32-bit
16-bit