CONTENTS
iv EPSON ARM720T CORE CPU MANUAL
List of Figures
Figure 1-1 720T Block diagram .................................................................................... 1-2
Figure 1-2 ARM720T processor functional signals....................................................... 1-3
Figure 1-3 ARM instruction set formats ........................................................................ 1-7
Figure 1-4 Thumb instruction set formats................................................................... 1-14
Figure 2-1 Big-endian addresses of bytes with words.................................................. 2-2
Figure 2-2 Little-endian addresses of bytes with words ............................................... 2-3
Figure 2-3 Register organization in ARM state.............................................................2-5
Figure 2-4 Register organization in Thumb state ......................................................... 2-6
Figure 2-5 Mapping of Thumb state registers onto ARM state registers ...................... 2-7
Figure 2-6 Program status register format....................................................................2-8
Figure 3-1 MRC and MCR bit pattern...........................................................................3-2
Figure 3-2 ID Register read format............................................................................... 3-3
Figure 3-3 ID Register write format .............................................................................. 3-3
Figure 3-4 Control Register read format ....................................................................... 3-4
Figure 3-5 Control Register write format ...................................................................... 3-4
Figure 3-6 Translation Table Base Register format...................................................... 3-5
Figure 3-7 Domain Access Control Register format ..................................................... 3-6
Figure 3-8 Fault Status Register format ....................................................................... 3-6
Figure 3-9 Fault Address Register format .................................................................... 3-7
Figure 3-10 FCSCE PID Register format ....................................................................... 3-8
Figure 3-11 PROCID Register format............................................................................. 3-8
Figure 6-1 Simple AHB transfer.................................................................................... 6-2
Figure 6-2 AHB bus master interface ........................................................................... 6-4
Figure 6-3 Simple memory cycle .................................................................................. 6-5
Figure 6-4 Transfer type examples............................................................................... 6-6
Figure 7-1 Translation Table Base Register.................................................................7-4
Figure 7-2 Translating page tables............................................................................... 7-5
Figure 7-3 Accessing translation table level one descriptors .......................................7-6
Figure 7-4 Level one descriptor.................................................................................... 7-6
Figure 7-5 Section descriptor ....................................................................................... 7-8
Figure 7-6 Coarse page table descriptor ...................................................................... 7-8
Figure 7-7 Fine page table descriptor........................................................................... 7-9
Figure 7-8 Section translation..................................................................................... 7-10
Figure 7-9 Level two descriptor ..................................................................................7-10
Figure 7-10 Large page translation from a coarse page table...................................... 7-12
Figure 7-11 Small page translation from a coarse page table...................................... 7-13
Figure 7-12 Tiny page translation from a fine page table ............................................. 7-14
Figure 7-13 Domain Access Control Register format ................................................... 7-17
Figure 7-14 Sequence for checking faults .................................................................... 7-19
Figure 8-1 Coprocessor busy-wait sequence ............................................................... 8-6
Figure 8-2 Coprocessor register transfer sequence ..................................................... 8-7
Figure 8-3 Coprocessor data operation sequence .......................................................8-7
Figure 8-4 Coprocessor load sequence ....................................................................... 8-8
Figure 8-5 Example coprocessor connections ............................................................. 8-9
Figure 9-1 Typical debug system ................................................................................. 9-2
Figure 9-2 ARM720T processor block diagram............................................................ 9-3
Figure 9-3 Debug state entry........................................................................................ 9-5
