1: Introduction
ARM720T CORE CPU MANUAL EPSON 1-7
1.3.2 ARM instruction set
This section gives an overview of the ARM instructions available. For full details of these
instructions, see the
ARM Architecture Reference Manual
.
The ARM instruction set formats are shown in Figure 1-3.
Figure 1-3 ARM instruction set formats
Note: Some instruction codes are not defined but do not cause the Undefined instruction
trap to be taken, for example, a multiply instruction with bit 6 set. You must not
use these instructions, because their action might change in future ARM
implementations.
Data processing
immediate
Multiply long
Load/store halfword/
signed byte
Load/store halfword/
signed byte
Load/store multiple
Branch and branch with
link
Coprocessor load and
store
Coprocessor data
processing
Coprocessor register
transfers
Software interrupt
0
0
0
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
0
1
1
1
0
P
P
P
0
0
1
1
U
U
U
0
1
A
W
W
S
L
L
P U S W L
Multiply
0 0 0 0 0 0 A S
L 24_bit_offset
Rd
RdHi
Rn
Rn
Rn
U N W L Rn
op1
op1
swi_number
L
Rn
RdLo
Rd
Rd
Register list
Rs
CRn
CRn
CRd
CRd
Rd
cp_num
cp_num
cp_num
Rn
1 0 0 1
1 0 0 1
SBZ 1 S H 1
High offset 1 S H 1
Rm
Rm
Rm
Rm
Low offset
8_bit_offset
op2
op2
0
1
CRm
CRm
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Data processing
immediate shift
0 0 0 opcode S Rn Rd shift immediate shift 0 Rm
Data processing register
shift
0 0 0 opcode S Rn Rd Rs shift 1 Rm0
Move fromstatus register
0 0 0 1 0 R 0 0 SBO Rd SBZ
Move immediate to status
register
0 0 1 1 0 R 1 0 Mask SBO rotate immediate
Move register to status
register
0 0 0 1 0 R 1 0 Mask SBO SBZ Rm0
Branch/exchange
instruction set
0 0 0 1 0 0 1 0 SBO SBO SBO Rm10 0 0
Load/store immediate
offset
0 1 0 P U B W L Rn Rd immediate
Load/store register offset
0 1 1 P U B W L Rn Rd shift immediate shift 0
Swap/swap byte
0
0
0 1 0 B 0 0 Rn Rd 1 0 0 1SBZ Rm
Undefined
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
cond
0 0 1 op S Rn Rd rotate immediatecond
0 1 1 x 1x x x x x x x x x x x x x x x x x x x x x x xcond
