MB39A105
14
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SETTING TIME CONSTANT FOR TIMER-LATCH SHORT-CIRCUIT PROTECTION CIRCUIT
The error amplifier’s output level alaways does the comparison operation with the short-circuit protection com-
parator (SCP Comp.) to the reference voltage.
While DC/DC converter load conditions are stable, the short-circuit detection comparator output remains stable,
and the CSCP terminal (pin 2) is held at soft-start end voltage (about 0.8 V) .
If the load condition changes rapidly due to a short-circuit of the load and the DC/DC converter output voltage
drops, the output of the error amplifier usually goes over 0.9 V. In that case, the capacitor C
SCP is charged further.
When the capacitor C
SCP is charged to about 1.0 V, the latch is set and the external FET is turned off (dead time
is set to 100%). At this time, the latch input is closed and the CSCP terminal (pin 2) is held at “L” level. When
CSCP terminal becomes “L” level, SCPOD terminal Nch MOS FET becomes OFF. SCPOD terminal (pin 4) is
held at “L” level and can be used as a short-circuit operating detection signal during normal operation.
To reset the actuated protection circuit, the power supply turn off and on again to lower the VCC terminal (pin
3) voltage to 1.1 V (Min) or less.
Short-circuit detection time (t
CSCP)
t
CSCP (s) := 0.23 × CSCP (µF)
−
−
+
−
+
−
+
FB
R1
R2
V
O
−INE
CSCP
(0.88 µA)(10.1 µA)
(1.0 V)
(0.5 V)
(0.9 V)
to Drive
VREF
VREF
SR
Latch UVLO
Error
Amp
SCP
Comp.
8
1
2
•
Timer-latch short-circuit protection circuit
